I. Field
The present invention relates generally to electronics, and more specifically to digital signal processors (DSPs) with configurable multiply-accumulate (MAC) units and arithmetic logic units (ALUs).
II. Background
DSPs are specialized microprocessors that are specifically designed to execute mathematical computations very rapidly. DSPs are widely used in a variety of electronic units such as compact disc players, PC disk drives, modem banks, audio devices, cellular phones, and so on. In cellular phones, the demand for DSP computation capability continues to grow, driven by the increasing needs of applications such as 3G (3rd generation) modem processing, position determination, image and video processing, 3-D gaming, and so on. These applications require DSPs that can perform computations quickly and efficiently.
A DSP typically contains a MAC unit and an ALU. The MAC unit is used for multiply-accumulate operations, which are commonly used in filtering and signal processing. The ALU is used for addition, subtraction, logical, shift, and bit-manipulation operations. A DSP may also contain multiple MAC units for higher computational throughput. An exemplary dual-MAC DSP architecture is described in U.S. Pat. No. 6,557,022, entitled “Digital Signal Processor with Coupled Multiply-Accumulate Units,” issued Apr. 29, 2003.
The goals of any DSP design are to (1) achieve the highest number of operations per unit time and (2) provide flexibility to perform different types of operations concurrently to allow for better utilization of the available hardware. DSP architectures that can satisfy these goals are highly desirable for meeting the processing demands of modern-day applications.